1. Field of the Invention
The present invention relates to processes for manufacturing semiconductor devices, and more particularly to a process for forming a contact in a MOSFET, a DRAM, etc.
2. Prior Art
Recently, increases in the integration density and capacity of so called MOS type DRAMs have been speeded up by the advancement of semiconductor techniques and more particularly by the advancement of the fine-working techniques.
By such increase in the integration density, the area of capacitors which store information (electric charges) decreases, and as a result, for example, a soft error arises in which the contents of a memory are read erroneously or destroyed by .alpha.-rays, etc.
Many methods are proposed which include the steps of forming storage nodes on a silicon substrate and increasing the area occupied by the capacitors, their capacitance and hence a quantity of electric charges stored in the capacitors to thereby increase the integration of such DRAMs.
To this end, a memory cell structure called a layered type memory cell is proposed in which a MOS capacitor is layered on a memory cell area, one electrode of the capacitor and one electrode of a switching transistor formed on the semiconductor substrate are rendered conductive thereacross to thereby increase the static capacitance of the MOS capacitor substantially.
As shown in FIGS. 26(a)-26(c), the layered-type memory cell includes a switching MOSFET as a transistor constituted by source and drain regions 104a and 104b of n-type diffusion layer, and a gate electrode 106 provided via a gate insulating film 105 between the source and drain electrodes 104a and 104b in one of two areas into which a p-type silicon substrate 101 is divided by an element separating insulator film 102. A capacitor is provided which includes a first capacitor electrode 110 and a second capacitor electrode 112 and an insulator film 111 held therebetween, the first capacitor electrode 110 being formed so as to contact the source region 104a of the MOSFET and so as to overlie the gate electrodes (or word lines) of the MOSFET and of a MOSFET of an adjacent memory cell via the insulator film 2.
The layered-type memory cell is formed as follows. In the cell, the MOSFET is formed as the switching transistor by forming the source and drain regions 104a and 104b of an n-type diffusion layer and the gate electrode 106 via the gate insulating film 105 between the source and drain regions 104a and 104b in the p-type silicon substrate 101.
A silicon oxide film is formed as an insulator film 107 on the whole substrate surface, and a storage node contact 108 is formed contacting the drain region 104b to form a pattern of the first capacitor electrode 110 of densely doped polycrystalline silicon layer.
A capacitor insulator film 111, for example, of silicon oxide, and a polycrystalline silicon layer are then deposited sequentially on the first capacitor electrode 110.
Thereafter, ions, for example, of phosphorus, are implanted into the polycrystalline silicon layer, which is then subjected to heat treatment at a temperature of about 900.degree. C. for 120 minutes to thereby form a polycrystalline silicon layer doped densely so as to have a desired conductivity.
The polycrystalline silicon layer is patterned to form a capacitor including the first and second capacitor electrodes 110 and 112 with the insulator film 111 therebetween.
Finally, an inter-layer insulator film 107' is formed, a bit line contact 113 is formed and a bit line is formed, for example, of molybdenum polycide. An inter-layer insulator film 107" is then formed on the film 107' to thereby provide the memory cell including the MOSFET and capacitor.
By such structure, the storage node electrode is expanded to over the device separating region and a step in the storage node electrode can be used, so that the capacity of the capacitor is increased to several-tens times that of a planar structure.
In order to provide a layered-type memory cell having an increased capacitor pattern area, a method is proposed which includes the steps of forming a switching transistor, a bit line and a capacitor in this order, as shown in FIGS. 27(a)-(c).
The layered-type memory cell is formed as follows. As in the memory cell shown in FIG. 26, the MOSFET is formed as the switching transistor by forming the source and drain regions 204a and 204b of an n-type diffusion layer and the gate electrode 206 via the gate insulating film 205 between the source and drain regions 204a and 204b in the p-type silicon substrate 201.
A silicon oxide film is formed as an insulator film 207 on the whole substrate surface, and a bit line contact 213 is formed contacting the source region 204a, a pattern of a bit line 214 is formed, for example, of molybdenum polycide.
An inter-layer insulator film 207' is then formed and a storage node contact 208 is formed to contact the drain region 204b to thereby form a pattern of the first capacitor electrode 210 of a densely doped polycrystalline silicon layer.
A capacitor insulator film 211, for example, of silicon oxide, and a polycrystalline silicon layer are then deposited sequentially on the first capacitor electrode 210.
Thereafter, ions, for example, of phosphorus, are implanted into the polycrystalline silicon layer, which is then subjected to heat treatment at a temperature of about 900.degree. C. for 120 minutes to thereby form a polycrystalline silicon layer doped densely so as to have a desired conductivity.
The polycrystalline silicon layer is patterned to form a capacitor including the first and second capacitor electrodes 210 and 212 with the insulator film 211 therebetween. The second capacitor electrode 210 is formed on the entire surface of the substrate.
Finally, an inter-layer insulator film 207" is then formed on the film 207' to thereby provide the memory cell including the MOSFET and capacitor.
Since in the particular arrangement the storage node electrode is expanded in the direction of extension of the bit line contact, the capacitor capacity is increased compared to the memory cells shown in FIG. 26.
However, even in the DRAM of such layered-type memory cell structure, the distance between the storage node contact and the gate electrode (shown by l1 in FIG. 26(a) and FIG. 27(a)) and the distance between the bit line contact and the gate electrode (l2 in FIG. 26(a) and FIG. 27(a)) must be decreased as finer devices are manufactured as a result of an increase in the integration density. Therefore, a short circuit is likely to occur between the storage node and the gate electrode and between the bit line and gate electrode to thereby reduce reliability.
The problem of a reduced distance between the contact and gate electrode applies to the pattern of the memory cells as well as to any of all the pattern of peripheral circuits.
FIG. 28 shows an illustrative transistor in a peripheral circuit. As the fining of such a peripheral circuit advances, the distances l3, l4 between the gate electrode and adjacent contact to thereby raise a problem of short circuit.
It is therefore an object of the present invention to provide a miniaturized highly reliable memory cell structure which prevents a short circuit from occurring between the storage node and the gate electrode, between the bit line and the gate electrode or between a lead for each of contacts in peripheral circuits and the gate electrode in spite of reduction of an area which the memory cell occupies, and a process for manufacturing such memory cell structure.